Design of a High-Performance DC Power Cycling Test Setup for SiC MOSFETs




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Institute of Electrical and Electronics Engineers Inc.


In this paper, a high-performance DC power cycling setup dedicated for SiC power MOSFETs is presented. Different from the previous DC power cycling setup designs focusing on circuit topology and operation principle, this paper discusses the detailed design considerations to ensure the measurement accuracy and control the voltage spikes within the safe voltage range of the data acquisition (DAQ) equipment. Specifically, the transient behavior of the circuit is analyzed, and a simulation model is built in LTspice to facilitate the design. From the simulation result, it is observed that the gate timing control is critical to limit the measurement spikes. In addition, adding decoupling capacitors helps to attenuate the ringing noise in the voltage measurement. A prototype is built, and the experimental results indicate that a precise measurement can be realized with the proposed DC power cycling setup under various conditions. © 2019 IEEE.


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Acquisition of data sets, Silicon carbide, Silicon compounds, Electric power transmission--Direct current, Capacitors, Metal oxide semiconductor field-effect transistors

National Science Foundation under the Award Number 1454311; Texas Analog Center of Excellence (TxACE) under the Task ID 2712.026


©2019 IEEE