High-Speed and Low-Power Pipelined SAR ADCs with Passive Residue Transfer and Dynamic Amplifier

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High-Speed and Low-Power Pipelined SAR ADCs with Passive Residue Transfer and Dynamic Amplifier

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Title: High-Speed and Low-Power Pipelined SAR ADCs with Passive Residue Transfer and Dynamic Amplifier
Author(s):
Huang, Hai
Advisor: Chiu, Yun
Date Created: 2017-05
Format: Dissertation
Keywords: Successive approximation analog-to-digital converters
Pipelined ADCs
Amplifiers (Electronics)
Abstract: High speed analog to digital converters (ADCs) are critical blocks in wideband wireline and wireless communication systems. This dissertation presents the designs of two high-speed pipelined successive-approximation-register (SAR) ADCs with the passive residue transfer technique and the process, voltage and temperature (PVT) stabilized dynamic amplifier. The passive residue transfer technique can effectively and efficiently replace the bandwidth-limiting residue amplifier in the medium-resolution pipelined SAR ADC. As a result, the time and power consumption associated with residue amplification are mostly removed and the ADC can obtain considerable speed improvement. Although dynamic amplifiers are employed in recent published pipelined SAR ADCs to achieve fast residue amplifications, the gain instability still limits the ADC's conversion accuracy when the supply voltage and ambient temperature varies. A PVT-stabilized dynamic amplifier based on the replica technique is reported to mitigate the gain variation over process, voltage and temperature changes. The first design is an 8 bit 1.2 GS/s pipelined SAR ADC with the passive residue transfer. It also utilizes the 2b-1b/cycle hybrid conversion scheme with an appropriate resolution partition to further enhance the conversion speed. The prototype ADC measured a signal-to-noise plus distortion ratio (SNDR) of 43.7 dB and a spurious-free dynamic range (SFDR) of 58.1 dB for a Nyquist input. The ADC consumes the total power dissipation of 5.0 mW and achieves a Walden FoM of 35 fJ/conversion-step at a sample rate of 1.2 GS/s. Although it is fabricated with a 65 nm process, the prototype ADC still achieves the same conversion speed as prior research works fabricated in a 32 nm process. The PVT-stabilized dynamic amplification technique is experimentally validated by the second ADC which is a 12 bit 330 MS/s pipelined-SAR ADC also in 65 nm CMOS. The maximum measured gain variations are 1.5% and 1.2% for the supply voltage varying from 1.25 V to 1.35 V and the temperature varying from −5 ºC to 85 ºC, respectively; the corresponding SNDR variations of the ADC are <1 dB. This prototype ADC measures an SNDR of 63.5 dB and a Walden FoM of 15.4 fJ/conv.-step for a near-Nyquist input. The conversion speed of this prototype ADC is 65% faster than the pipelined SAR ADCs with a similar SNDR published recently.
Degree Name: PHD
Degree Level: Doctoral
Persistent Link: http://hdl.handle.net/10735.1/5793
Terms of Use: ©2018 The Author. Digital access to this material is made possible by the Eugene McDermott Library. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Type : text
Degree Program: Electrical Engineering

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